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CMOS Frequency Synthesizer For 40 Gb/s Serial Optical Link

This work is part of the HIGHSCORE (High Speed Communication Receiver in CMOS for 40 Gb/s Serial Optical Link) KTI Project 6726.1 FHS.

Project Partners

High-Speed Interconnect Technology Group at IBM Research Laboratory, Rüschlikon
Zentrum für Mikroelektronik Aargau, Windisch Project Managment of HIGHSCORE
Berner Fachhochschule

PLL Phase Generator

A sub-rate clock recovery system samples incoming data at data rate N with k equally spaced phases of a clock signal of frequency N/k. A half rate approach with k = 2 is a good compromise between complexity and technology requirements and seems to be the optimum for this project. However, a full rate approach may also be possible and should be evaluated. The PLL frequency generator consists of a high frequency multi phase VCO (voltage controlled oscillator), a frequency divider module, a low frequency quartz reference PLL and a buffer.

Multi Phase VCO
For the generation of multiphase clock signals a number of approaches are possible, e.g. LC-tuned multi phase oscillators, multi phase ring oscillators, frequency division from an ultra-high-speed oscillator, and active or passive multiphase networks. These topologies have different properties in terms of phase accuracy, frequency stability, jitter (phase noise), amplitude stability, power consumption and more. Thus, these approaches must be carefully examined and the best solution must be found - again under the consideration of power minimization and low voltage operation. A suitable voltage controlled oscillator with multiple phases will be designed according to the result of the topology investigation. All phases should be equally spaced. Variations of the phase differences and jitter in the oscillation signals would degrade the system performance.

Frequency Divider Module
Delay locked loops do not have large frequency acquisition ranges and must therefore be stabilized by a highly accurate quartz referenced oscillator signal. This is accomplished by an additional PLL locking the high-speed multiphase oscillator to the quartz reference. For this task the high frequency signal has to be down converted by a frequency divider module.

Quartz Reference
The required quartz reference PLL consists of a phase/frequency detector, a low pass filter and a low frequency VCO, which is resonated by an external reference quartz.

A buffer has to be co-designed with the phase rotator to match the corresponding interface specifications. A preservation of the generated reference phases is mandatory, thus requiring careful layout.

George von Büren, PhD student of the ETH RFIC group, is in charge of this topic.

Sampling Block (Latches and Phase Rotator)

System evaluations are important for the sampling block since interface characteristics and specifications e.g. between the optical front-end, the fixed frequency PLL and the DEMUX part have to be considered. Different sub system topologies have to be investigated to minimize the power consumption and to optimize the dynamic range. The DLL (delay-locked loop) approach is well suited for this project, since in comparison to other methods of clock- and data recovery, the loop filter can be implemented as a fully digital filter. No external components (capacitors or inductors) are needed. Thus, the implementation of several parallel links on a single chip is possible. However, the tradeoffs of other approaches should be evaluated and compared. The sampling block mainly consists of the sampling latches, the phase rotator and the interface buffers.

The latches are the most speed critical elements in the clock/data recovery circuit because they have to run at the highest data rate. Their rise and fall times must be sufficiently short for the full data rate of 40 Gb/s. Therefore, they have to be designed very carefully with emphasis on the dynamic behavior. The performance and system compatibility of different approaches such as e.g. level controlled, edge controlled and multilevel detection latches will be investigated and compared.

Phase Rotator
In the phase rotator, all reference phases generated by the PLL phase generator are shifted in order to lock the control loop. The amount of the phase shift needed is given by the digital control logic. All phases have to be shifted by the same amount. Additional phase shifts of a single phase due to the phase rotator circuit or its layout directly degrade the system performance. Hence, this building block must be designed very carefully with respect to signal propagation times. A further critical issue of the phase rotator is pick-up of noise: The output of this block will comprise many parallel signal lines with shifted versions of original clock phases. Noise or any other feed-through of unwanted signals into this block can severely limit the overall system's jitter performance. Different vector modulator and delay line based phase shifter topologies should be investigated and compared. Digital adjustable approaches should be preferred. However, continuously adjustable approaches may be investigated to evaluate the obtained improvement of the phase precision.

Input and Output Buffers
Input and output buffers have to be designed to provide the optimum interface characteristics for the optical front-end, the loop filter and the DEMUX part. The minimization of the power consumption is a mandatory design goal.

Lucio Rodoni, PhD student of the ETH RFIC group, is in charge of this topic.
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